Project Viva Voce & Industry Oriented Mini-Project - date

Dear Students,

The final year IoMP and Project Viva will be conducted by Dr. Gurram Ravindra Babu, Professor, Keshav Memorial Institute of Technology.

The date is 08-04-2011.
Reporting time : 9:00AM for section A students and 01:00PM for section B students

Professor GR Babu , is 75 years young and loves teaching. He did his PhD in Microwaves from BITS Pilani and is a father figure to many  eminent personalities in the field of Electronics.

Dr. GR Babu worked in BITS, SV University , JNTU (Hyderabad), GNITS and a few other Engineering colleges. Dr Babu , you  will be interested to know was the key personality to take SVIT  ECE Department into his arms and nurture the department to its present stage. All that you see in the ECE Department is because of his hard work - be it the faculty or the  equipment in the labs.

Dr GR Babu taught EMTL and AWP in JNTUH (then at Masab Tank campus) and I was fortunate to be his student during my B.Tech (1976-1981)...then  a 5 year course.

Dr Babu will be visiting our campus after a long time.

The panel will consist of Dr. GR Babu, Internal Guide and HoD along with another senior faculty.

Good Wishes

Visit by MyGo & SprihaIT

Dear Students,


Tomorrow ,


1. Director of MyGo Informatics Mr. G. Rahul will come to and meet the students doing project with MyGo.
    He will come @ 2pm.
2. The zonal manager of SprihaIT Mr. Raju will be coming  around 12noon to meet SprihaIT project students.
*********************************************************************************
The tentative plan is to ask one representative from each project batch - around 20 students to meet him and give feedback pending issues.
After this meeting, I will not entertain any issues related to your project and we will directly proceed to project viva.
Please treat this meeting as EXTREMELY important and prepare well to interact professionally with the director.
Each student must speak for 1-2 mts without repeating what has been already told.
Then, we will have an interactive session.
I will be there to take notes.


Good Wishes

Technical Seminar

There are 25 students who are yet to give their technical seminar.
You are now required to met K.Karthik sir, check the timing and then give your presentation.


No more names in this list.


Good Wishes

ERTS Questions for the exam

Embedded and Real Time Systems
1	Explain briefly about the Architecture of the kernel?
2	Explain about Tasks States in detail?
3	Explain Context Switching in detail?
4	Explain Round Robin   Scheduling Algorithms?
5	Explain Nonpreemptive Multitasking Algorithms?
6	Explain preemptive Multitasking Algorithms?
7	Explain briefly about rate monotonic analysis?
8	Explain Semaphore Management and Mutex Management Function Calls in detail ?
9	Explain Mailbox Management Function Calls in detail?
10	Explain Message Queue Management Function Calls in detail?
11	Define Signals? Explain Signal Management Function Calls in detail?
12	Explain Event Registers Management Function Calls in detail?
13	Explain Inter Task Communication using pipes?
14	Explain in detail about Priority Inversion problem?
15	Explain in detail about priority Inheritance?
16	List various Embedded operating Systems and explain their features?
17	List various Real Time operating Systems and explain their features?
18	List various Handheld operating Systems and explain their features?
19	Explain in Detail about Hardware-Software Co-design?
20	What is an Emulator? Mention its Usage in Embedded System Design?

Verilog HDL Questions

Questions from Verilog HDL

Units 5-8

1. What are the different system tasks ? Briefly explain each one.
2. List the compiler directives in Verilog and explain the purpose of each one.
3. Define a function using a structure. Give an example program.
4. What is the scope of functions ?
5. What are recursive functions ?
6. Define a task. How can tasks be enabled ? Give an example.
7. Hoe are user defined primitives (UDP) instantiated ? Give an example.
8. Are UDP and functions similar ? Different ? Substantiate your answer.
9. Write the UDP for an Edge Triggered Flip-Flop.
10. Explain in detail the process of digital design with SM Charts.
11. How are SM charts realized ?  Give examples.
12. Explain linked State machines in detail.
13. Show how a dice game is implemented.
14. Explain the features of XILINX 3000 series FPGAs in detail.
15. Explain the features of Altera CPLDs with reference to FLEX 10K Series.
16. Compare and contrast XILINX architecture with Altera.
17. Explain how you would use Verilog to model the following :
1. Static RAM memory.
2. 80486 simplified Bus
3. UART
4. Microcontroller

Technical Seminar : Plan for evaluation

If your topic is accepted and you have got a mail from me about this, then :


1. Please be prepared to give your seminar on the day AFTER your Comprehensive viva is over.


Eg: If your HT No is between 401 and 420 and your  Topic is ACCEPTED. 
Then, your Tech Seminar will be on 16th.


Please note this and inform all your class mate.


HoD-ECE-SVIT